Flat panel display

ABSTRACT

The present invention discloses an organic light emitting device for preventing element defects and improving picture quality by reducing a taper angle of a substrate surface. The flat panel display of the present invention comprises, an insulating substrate, a lower layer formed on the insulating substrate and having a first step and a first taper angle with respect to the substrate surface, and an upper layer formed on the insulating substrate and for reducing the taper angle of the lower layer. The upper layer has a second taper angle smaller than the first taper angle of the lower layer. The upper layer is a conductive layer that may be applied by a wet coating method, has a charge transporting capability, and is selected from at least one of a small-molecule organic layer including a carbazole-based, arylamine-based, hydrazone-based, stilbene-based, oxadiazole-based, starburst-based derivatives, and a polymer organic layer including PEDOT, PANI, carbazole-based, arylamine-based, perylene-based, pyrrole-based, oxadiazole-based derivatives.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of Korea Patent Application No.2003-84746, filed on Nov. 26, 2003, the disclosure of which isincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a flat panel display and, moreparticularly, to an active matrix organic light emitting device capableof avoiding a defective element and improving picture quality byreducing a taper angle of a substrate surface.

2. Background of the Invention

In general, pixels in an active matrix organic light emitting device(AMOLED) are arranged on the substrate in a matrix form. Each pixelincludes an electroluminescence (EL) element, where an anode electrode,an organic film layer and a cathode electrode are stacked, and a thinfilm transistor (TFT) as an active element connected to the EL elementand for driving the EL element.

FIG. 1A shows a cross-sectional view of a conventional bottom-emittingOLED. Referring to FIG. 1A, a semiconductor layer 110 has a buffer layer105 formed on an insulating substrate 100 and source and drain regions111 and 115 formed on the buffer layer 105. A gate 125 is formed on agate insulating layer 120, and source and drain electrodes 141 and 145are formed on an inter-layer insulating layer 130 through contact holes131 and 135, to be connected to the source and drain region 111 and 115,respectively. As a result, the TFT is fabricated. Wiring 147, such as adata line or a power supply line, is formed on the inter-layerinsulating layer 130.

An anode electrode 170, as a lower electrode connected to the drainelectrode 145 through a via hole 155, is formed on a passivation layer150, and an organic film layer 185 and a cathode electrode 190, as anupper electrode, are formed on the substrate, thereby fabricating theorganic EL element.

FIG. 1B shows a detailed cross-sectional view of the red on R pixel ELelement within an emission region of an R pixel in the OLED of FIG. 1A.A method for fabricating the EL diode is described in detail below, withreference to FIG. 1B. A cleaning process is performed after forming theanode electrode 170 connected to the drain electrode of the TFT throughthe via hole 155. A 600 Å thick hole injecting layer 185 a is thenformed with CuPc on the substrate using a vacuum deposition method, anda 300 Å thick hole transporting layer 185 b is formed with NPB on thehole injecting layer 185 a. A 200 Å thick Alq+DCM is deposited on thehole transporting layer 185 b to form a red color emission layer 185 c.A 200 Å thick Alq3 is formed on the red color emission layer 185 c toform an electron transporting layer 185 d, thereby forming the organicfilm layer 185. Finally, a LiF/Al, as the cathode electrode 190, isdeposited by a thermal evaporation method. Although not shown in thefigure, a hole blocking layer may be formed between the red coloremission layer 185 c and the electron transporting layer 185 d, or anelectron injecting layer may be formed on the electron transportinglayer 185 d.

After forming the organic film layer 185 and the cathode electrode 190on the anode electrode 170, as shown in FIG. 1B, a sealant (not shown)is applied on the insulating substrate 100, and an encapsulatingsubstrate is bonded to the insulating substrate to prevent externaloxygen and moisture from being introduced inside, thereby fabricatingthe conventional OLED.

The conventional OLED having the above mentioned structure may havepinhole defects occurring near a stepped portion of the anode electrode160, near the via hole 155 and near the contact holes 141 and 145,and/or short-circuit defects between the anode and cathode electrodes.Furthermore, portions where the organic emission layer is not depositedor not uniformly deposited may be thinner than other portions near thestepped portion of the anode electrode and near the contact holes andvia holes. When a high voltage is applied between the anode and cathodeelectrodes, a current density may focus on the portion where the organicemission layer is not deposited or is thinly deposited, so that one ormore spherical dark spot may occur. As a result, the emission region maydecrease and the picture quality may deteriorate due to the occurrenceof the dark spot.

Oxygen and/or moisture may be more easily introduced through a portionwhere the cathode electrode is not densely formed. When a high voltageis applied between the anode and cathode electrodes, a current densityis focused on the portion where the cathode electrode is not denselyformed, and a void occurs in the cathode electrode due to anelectromigration. Heat may occur due to increased resistance from anexternal oxygen inflow. As a result, a spherical dark spot may occur inthe portion as time passes.

To prevent defects, such as a short-circuit or the dark spot, a contacthole or via hole may be formed having a small taper angle. However,there has been a limit in reducing the taper angle of the contact holeor via hole due to difficulties in design of a high resolution flatpanel display.

U.S. Pat. No. 5,684,365 discloses a technique that limits a taper angleof a passivation layer at an edge of an opening for exposing someportions of the anode electrode. FIG. 2 illustrates a cross-sectionalview of a conventional bottom-emitting OLED. Referring to FIG. 2, abuffer layer 205 is formed on an insulating substrate 200, and asemiconductor layer 210 having source and drain regions 211 and 215 isformed on the buffer layer 205. A gate 225 is formed on a gateinsulating layer 220, and source and drain electrodes 241 and 245 areformed to be connected to the source and drain regions 211 and 215,respectively, through contact holes 231 and 235 on an inter-layerinsulating layer 230. In this case, an anode electrode 270, as a lowerelectrode to be connected to the drain electrode 245, is formed on theinter-layer insulating layer 230.

After depositing a passivation layer 250, at a thickness of 0.5 to 1.0μm formed of an insulating layer, such as an silicon nitride layer, on asubstrate, the passivation 250 is etched to form an opening 275 exposingsome portions of the anode electrode 270. In this case, the passivationlayer 250 is formed to have a taper angle of 10 to 30° with respect tothe anode electrode at an edge of the opening 275. An organic film layer285 and a cathode electrode 290 as an upper electrode are then formed onthe substrate. The organic film layer 285 has at least one of a holeinjecting layer, a hole transporting layer, an R, G, or B emissionlayer, a hole barrier layer, an electron transporting layer, or anelectron injecting layer, as shown in FIG. 1B.

U.S. Pat. No. 6,246,179 discloses a technique that uses an organicinsulating layer having a planarizing function to prevent defects fromoccurring near a via hole or a contact hole and at a stepped portion.FIG. 3 shows a cross-sectional view of the OLED having a conventionaltop-emitting structure. Referring to FIG. 3, a buffer layer 305 isformed on an insulating substrate 300, and a semiconductor 310, havingsource and drain regions 311 and 315, is then formed on the buffer layer305. A gate 325 is formed on a gate insulating layer 320, and source anddrain electrodes 341 and 345 are connected to the source and drainregions 311 and 315, respectively, through contact holes 331 and 335 onan inter-layer insulating layer 330. In this case, wiring 347, such as adata line or a power supply line, is formed at the same time the sourceand drain electrodes 341 and 345 are formed on the inter-layerinsulating layer 330.

A planarization layer 360 is formed on a passivation layer 350, and ananode electrode, as a lower electrode, is connected to one electrode,for example, to the drain electrode 345 between the source and drainregions 341 and 345 through the via hole 355 on the planarization layer360. A pixel defining layer 365, having an opening 375 for exposing someportions of an anode electrode 370, is formed, and an organic film layer385 and a cathode electrode 390 as an upper electrode are formed on thepixel defining layer 365 and the anode 370. The organic film layer 385has at least one of a hole injecting layer, a hole transporting layer, aR, G, or B emission layer, a hole blocking layer, an electrontransporting layer and an electron injecting layer, as shown in FIG. 1B.

As in the above mentioned conventional OLED, a taper angle of thepassivation layer connected to the anode electrode within the opening islimited to between 10° to 30°, or a taper angle of the pixel defininglayer is limited to between 20° to 80°, thereby preventing defects inthe organic emission layer. In addition, the problem of the steppedportion may be solved by using the planarization layer, therebypreventing the defect of the organic emission layer.

However, in the high-resolution OLED, there has been a limit to reducingthe taper angle of the passivation layer or the pixel defining layer dueto difficulties in the design process. Furthermore, the reliability ofthe element depends on a taper angle between the pixel defining layerand the anode electrode. When the taper angle is large, the organicemission layer and the cathode electrode easily deteriorate at the edgeof the opening. When the taper angle is small, there has been a limit toreducing the tape angle and thickness of the pixel defining layer due toproblems of parasitic capacitance and a stepped portion caused by thewiring.

In addition, since the cathode electrode deposited on the entire surfaceof the substrate is not densely formed near the contact hole, near thevia hole and at the stepped portion, as described above, dark spot mayoccur, or a pinhole or short-circuit defect may occur near the contacthole, near the via hole and at the stepped portion.

SUMMARY OF THE INVENTION

The present invention provides an OLED capable of preventing pinhole andshort-circuit defects in a contact hole and a via hole.

The present invention provides an OLED capable of improving a picturequality by reducing or preventing a pattern defect of an organic ELlayer.

The present invention provides an OLED capable of reducing or preventinginflow of oxygen or moisture by densely forming a cathode electrode.

The present invention provides an OLED capable of reducing or preventinga dark spot from being occurred in an emission region of a pixel.

An exemplary embodiment of the present invention provides a flat paneldisplay having an insulating substrate, a lower layer formed on theinsulating substrate and having a first step and a first taper anglewith respect to a surface of the substrate, and an upper layer formed onthe insulating substrate and for reducing the taper angle of the lowerlayer, wherein the upper layer has a second taper angle smaller than thefirst taper angle of the lower layer.

According to another exemplary embodiment of the present invention, aflat panel display includes an insulating substrate including a thinfilm transistor having at least source and drain electrodes, aninsulating layer formed on the insulating substrate and having a viahole for exposing one of the source and drain electrodes, an organic ELelement having a lower electrode, an organic film layer and an upperelectrode formed on the insulating layer and connected to the exposedone through the via hole, and a taper reducing layer formed on the lowerelectrode, wherein a taper angle of the taper reducing layer in the viahole has a first taper angle smaller than that of the via hole, and ataper angle of the taper reducing layer at an edge of the lowerelectrode has a second taper angle smaller than that of the edge of thelower electrode.

According to a further embodiment of the present invention, a flat paneldisplay includes an insulating substrate including a thin filmtransistor having at least source and drain electrodes, a firstinsulating layer formed on the insulating substrate and having a viahole for exposing one of the source and drain electrodes, a lowerelectrode formed on the first insulating layer and connected to theexposed one through the via hole, a second insulating layer having anopening for exposing a portion of the lower electrode, an organic filmlayer formed on the second insulating layer and the opening, an upperelectrode formed on the organic film layer, and a taper reducing layerformed on the lower electrode, wherein the taper reducing layer has ataper angle smaller than that of the second insulating layer in theopening.

In an additional exemplary embodiment of, the present invention, a flatpanel display includes an insulating substrate including a thin filmtransistor which includes a semiconductor layer having source and drainregions, a first insulating layer having contact holes for exposing someportions of the source and drain regions, and source and drainelectrodes connected to the source and drain regions through the contactholes, a second insulating layer formed on the insulating substrate andhaving a via hole for exposing one of the source and drain electrodes,an EL element formed on the second insulating layer to be connected toone electrode of the thin film transistor through the via hole andhaving a lower electrode, an organic film layer and an upper electrode,and a taper reducing layer formed on the lower electrode, wherein ataper angle of the taper reducing layer in the contact hole has a firsttaper angle smaller than that of the contact hole, a taper angle of thetaper reducing layer in the via hole has a second taper angle smallerthan that of the via hole, and a taper angle of the taper reducing layerat an edge of the lower electrode has a third taper angle smaller thanthat of the edge of the lower electrode.

According to a further exemplary embodiment of the present invention, aflat panel display includes an insulating substrate including a thinfilm transistor which includes a semiconductor layer having source anddrain regions, a first insulating layer having contact holes forexposing portions of the source and drain regions and source and drainelectrodes connected to the source and drain regions through the contactholes, and a second insulating layer formed on the insulating substrateand having a via hole for exposing one of the source and drainelectrodes. The flat panel display further includes a lower electrodeformed on the second insulating layer and connected to the exposed oneof the source and drain electrodes, a third insulating layer having anopening for exposing a portion of the lower electrode, an organic filmlayer formed on the third insulating layer and the opening, an upperelectrode formed on the organic film layer, and a taper reducing layerformed on the lower electrode, wherein a taper angle of the taperreducing layer in the opening is smaller than that of the opening.

An additional exemplary embodiment of the present invention provides aflat panel display includes an insulating substrate including a thinfilm transistor which includes a semiconductor layer having source anddrain regions, a first insulating layer having contact holes forexposing some portions of the source and drain regions and source anddrain electrodes connected to the source and drain regions through thecontact holes, a lower electrode formed on the same first insulatinglayer as the source and drain electrodes and connected to one of thesource and drain electrodes, and a second insulating layer having anopening for exposing a portion of the lower electrode. The flat paneldisplay also includes an organic film layer formed on the secondinsulating layer and the opening, an upper electrode formed on theorganic film layer, and a taper reducing layer formed on the lowerelectrode, wherein a taper angle of the taper reducing layer in thecontact hole have a first taper angle smaller than that of the contacthole, and a taper angle of the taper reducing layer in the opening has asecond taper angle smaller than that of the opening.

Still a further exemplary embodiment of the present invention provides aflat panel display including an insulating substrate, a lower layerformed on the insulating layer and having a first step and a first taperangle θ1 with respect to a surface of the substrate, and an upper layerformed on the insulating substrate and having a second taper angle θ2with respect to the substrate surface for reducing the first taper angleof the lower layer, wherein a deposition thickness d0 is the depositionthickness of the lower layer at the first step, a deposition thicknessd2 is the deposition thickness of the upper layer on the first step anda deposition layer d3 is the deposition thickness of the upper layer ata portion other than the first step, and a taper angle θ2 of the upperlayer are obtained from the equation below,tan θ2=(1−d 2/(d 1−d 0))tan θ1d 2=(d 1−d 0)(1−tan θ2/tan θ1)d 3=d 1(1−tan θ2/tan θ1),

-   -   wherein d1 is a deposition thickness of the upper layer when the        second taper angle of the upper layer becomes 0°.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent to those of ordinary skill in the art bydescribing in detail preferred embodiments thereof with reference to theattached drawings.

FIG. 1A illustrates a cross-sectional view of a conventional OLED.

FIG. 1B illustrates a cross-sectional view of an emission region of onepixel in the OLED shown in FIG. 1A.

FIG. 2 illustrates a cross-sectional view of a conventional OLED havinga pixel defiling layer.

FIG. 3 illustrates a cross-sectional view of a conventional OLED havinga passivation layer where the edge is tapered.

FIG. 4 illustrates a cross-sectional view of an OLED employing a taperreducing layer according to an embodiment of the present invention.

FIG. 5A illustrates a taper angle and a defect generation rate in anOLED that has not employed a taper reducing layer according to anembodiment of the present invention according to an embodiment of thepresent invention.

FIG. 5B illustrates a relationship between the taper angle and thethickness of the taper reducing layer in the OLED shown in FIG. 3.

FIG. 6A illustrates a cross-sectional view of a bottom-emitting AMOLEDin accordance with an embodiment of the present invention.

FIG. 6B illustrates a cross-sectional view of the emission region of onepixel in the bottom-emitting AMOLED shown in FIG. 6A.

FIG. 6C illustrates a cross-sectional view of the emission region of onepixel in the bottom-emitting AMOLED shown in FIG. 6A.

FIG. 7A illustrates the reduced taper angle by the taper reducing layerin the AMOLED shown in FIG. 6A.

FIG. 7B illustrates a pixel that the dark spot is not occurred in theAMOLED shown in FIG. 6A.

FIG. 7C illustrates that defects occur in the pixel when the taperreducing layer is not employed in the conventional bottom-emitting OLED.

FIG. 8 illustrates a cross-sectional view of a bottom-emitting AMOLEDhaving a pixel defining layer in accordance with an embodiment of thepresent invention.

FIG. 9A illustrates that the taper angle is reduced by the taperreducing layer in the AMOLED shown in FIG. 8.

FIG. 9B illustrates a pixel that the dark spot is not occurred in theAMOLED shown in FIG. 8.

FIG. 9C illustrates a pixel where dark spots occur in an OLED having aconventional pixel defining layer.

FIG. 10 illustrates a cross-sectional view of a top-emitting AMOLED inaccordance with a third embodiment of the present invention.

FIG. 11 illustrates a cross-sectional view of a top-emitting AMOLEDhaving a pixel defining layer in accordance with a fourth embodiment ofthe present invention.

FIG. 12 illustrates a cross-sectional view of an AMOLED in accordancewith an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which exemplary embodimentsof the invention are shown. This invention may, however, be embodied indifferent forms and should not be construed as limited to theembodiments set forth herein. Rather, these embodiments are provided sothat this disclosure will be thorough and complete, and will fullyconvey the scope of the invention to those skilled in the art. In thedrawings, the thickness of layers and regions are exaggerated forclarity. Like numbers refer to like elements throughout thespecification.

FIG. 4 illustrates a cross-sectional view of an OLED having a taperangle reduced by a taper reducing layer of the present invention.Referring to FIG. 4, an insulating substrate 40 has a lower layer 41having an opening 42 for exposing a portion of the insulating substrate40. The lower layer 41 has a predetermined taper angle with respect toan upper surface of the substrate at an edge of the opening 42.Furthermore, the lower layer 41 has a predetermined step d0 with respectto the upper surface of the substrate.

A taper reducing layer 43 having a taper angle θ2 is formed on the lowerlayer 41 and the opening 42. The deposition thickness of the taperreducing layer 43 may depend on the step of the substrate surface wherethe taper reducing layer is deposited. In other words, the taperreducing layer deposited on a portion where the substrate surface has ahigh step is deposited thinner than the taper reducing layer depositedon a portion where the substrate surface has a low step. Thus, the taperreducing layer 43 has a thickness of d2 on the lower layer having thestep d0, and has a thickness of d3, thicker than d2 on the opening 42,for exposing the substrate. Since the thickness of the taper reducinglayer 43 depends on the step of the substrate surface, the taperreducing layer 43 has a taper angle smaller than the taper angle at thelower layer 41. As a result, the taper reducing layer 43 has a taperangle θ2 smaller than the taper and θ1 of the lower layer 41.

In the OLED of an embodiment of the present invention, when the lowerlayer 41 is an insulating layer, such as an inter-layer insulating layerand a gate insulating layer, the opening 42 is a contact hole andexposes some portions of the source and drain regions. Thus, the taperangle of the contact hole becomes θ1, and the step formed by the contacthole in the insulating layer, with respect to the substrate surface, isd0.

When the lower layer 41 is a passivation layer, the opening 42 is a viahole and exposes a portion of the source and drain regions. Thus, thetaper angle of the via hole becomes θ1, and the step formed by the viahole in the passivation layer with respect to the substrate surface isd0. When the lower layer 41 is a pixel defining layer, the opening 42exposes a portion of a pixel electrode. Thus, the taper angle of thepixel defining layer at the edge of the opening becomes θ1, and the stepformed by the opening in the pixel defining layer with respect to thesubstrate surface is d0.

When the taper reducing layer 43 is formed within the contact hole, viahole, or opening of the pixel electrode, a conductive layer is formedover and below the taper reducing layer 43, so that the taper reducinglayer 43 is formed, for example, of a conductive material. An organiclayer that has a charge transporting capability and may be coated by awet coating method may be used for the taper reducing layer 43. Thetaper reducing layer 43 may consist of at least one organic layerselected from a polymer organic layer, a small-molecule organic layer orsimilar material. The small-molecule organic layer for the taperreducing layer may be selected from carbazole-based, arylamine-based,hydrazone-based, stilbene-based, oxadiazole-based and starburst-basedderivatives, and the polymer organic layer is selected from PEDOT, PANI,carbazole-based, arylamine-based, perylene-based, pyrrole-based andoxadiazole-based derivatives or similar materials.

In the above mentioned OLED, the principle that the taper angle isreduced by the taper reducing layer is as follows. The lower layer 41has an opening 42, such as the contact hole, via hole, or opening regionof the pixel defining layer, a step of d0 and a taper angle of θ1 withrespect to the substrate surface, and a linear slope of tan θ1. Thetaper reducing layer 43 has a thickness of d2 on the lower layer 41 andd3 on the opening 42, a taper angle of θ2, and a linear slope of tan θ2with respect to the substrate surface. In addition, the minimumthickness of the taper reducing layer required to planarize thesubstrate surface, i.e., the minimum thickness of the taper reducinglayer 43 required to have its taper angle θ2 of zero degree with respectto the substrate surface, is d1.

Thus, the taper angle planarized by the taper reducing layer 43 becomesθ2, which is the taper angle of the taper reducing layer 43 in theopening 42. The taper angle before it is planarized is θ1, which is thetaper angle of the lower layer 41 in the opening 42. When a straightline having a slope of tan θ1, formed by the taper angle θ1 of the lowerlayer 41, is assumed to be L1 and a straight line having a slope of tanθ2, formed by the taper angle θ2 of the taper reducing layer 43, isassumed to be L2, where L1 and L2 may be expressed as the equation 1below. In this case, a point where the substrate surface and thestraight line L1 meet, i.e., an edge portion of the opening 42, is anorigin O, where a longitudinal direction of the substrate is an x axis,and a height direction of the substrate is a y axis.L1:y1=tan θ1xL 2:y 2=tan θ2+d 3  (1)

The straight line L1 passes the d0 at the position x0 of the x axisdirection, and the straight line L2 passes the d0+d2 at a position x0 ofthe x axis direction. In addition, the lines L1 and L2 pass d1 at theposition x1 of the x axis direction.

Thus, when functions y1 and y2 are substituted with values of the x andy axis directions in the equation 1, the result is as follows.L1:d0=tan θ1x0L 2:d 0+d 2=tan θ2 x 0 +d 3

Thus, d0+d2 may be expressed as the equation 2 below.d 0+d 2=(tan θ2/tan θ1)d 0+d 3  (2)

In addition,L1:d1=tan θ1x1L 2:d 1=tan θ2×1+d 3

Therefore, d1 may be expressed as the equation 3 below.d 1=(tan θ2/tan θ1)d 1+d 3  (3)

From the equations 2 and 3, a relationship equation with respect to thetaper angle θ2 of the taper reducing layer 43 is obtained from theequation 4 below. Thickness d2 and thickness d3 of the taper reducinglayer 43 to be deposited on the lower layer 41 and the opening 42,respectively, are obtained from equations 5 and 6 below. The thicknessd2 of a portion of the taper reducing layer 43 formed on the lower layer41 may linearly increase until the thickness d1−d0, that is, thethickness when the substrate surface is planarized from the surface ofthe lower layer 41. The thickness d3 of a portion where the taperreducing layer 43 is formed in the opening 42 may linearly increaseuntil the thickness d1, namely, the thickness when the substrate surfaceis planarized from the surface of the opening 42. The minimum thicknessd1 required to planarize the substrate surface may vary in accordancewith the planarizing capability of the organic layer used for the taperreducing layer, and may be varied and experimentally obtained inaccordance with viscosity and volatility of a solution, variables of acoating process, and the like.tan θ2=(1−d 2/(d 1−d 0))tan θ1  (4)d 2=(d 1−d 0)(1−tan θ2/tan θ1)=(d 1−d 0)(1−α)  (5)d 3=d 1(1−tan θ2/tan θ1)=d 1(1−α)  (6)

In the above equations, α is a rate of a planarizing degree for thesubstrate surface when the taper reducing layer is formed on thesubstrate with respect to the planarizing degree of the substratesurface when the lower layer by itself is formed on the substrate. Thevalue is defined as a relative flatness, and is expressed as α=tanθ2/tan θ1.

For example, the lower layer 41 is an insulating layer having a via holeas the opening 42 and has a thickness of 6000 Å and a taper angle θ1 of75° in the via hole. When the minimum thickness d1 is experimentallyassumed to be 8000 Å to entirely planarize the via hole, the angle θ2with which the substrate surface is planarized by the taper reducinglayer 43 and the thickness d3 of the taper reducing layer 43 in the viahole are calculated as described below from the equations 4 and 6 above,to have the taper reducing layer 43 with 1000 Å in thickness to bedeposited on the lower layer 41.tan θ2=(1−1000/2000)tan 75=0.5*3.73=1.87

The taper angle θ2 of the taper reducing layer 43 in the via hole is asfollows.θ2=tan⁻¹(1.87)=62°.

In addition, the thickness d3 of the taper reducing layer 43 in the viahole is as follows.d 3=d 1(1−tan θ2/tan θ1)=d 1*d 2/(d 1−d 0)=8000*1000/2000=4000

Thus, when the taper angle of the via hole is 75° and the thickness ofthe taper reducing layer 43 formed on the lower layer 41 is 1000 Å, thethickness d3 of the taper reducing layer 43 formed in the via holebecomes 4000 Å.

In the meantime, when the taper reducing layer 43 is deposited to havethe angle planarized by the taper reducing layer 43, namely, the taperangle θ2 of the taper reducing layer 43 in the via hole to be below 40°or less, the thickness d2 of the taper reducing layer formed on thelower layer 41 and the thickness d3 of the taper reducing layer formedin the via hole are obtained as follows from the equations 5 and 6d 2=2000 (1−tan 40/tan 75)=2000 (1−0.23)=1540d 3=8000 (1−tan 40/tan 75)=8000 (1−0.23)=6160

In other words, when the taper reducing layer 43 in the via hole isformed to have the taper angle θ2 of 40°, it may be arithmetically seenthat the taper reducing layer 43 is formed with 1540 Å on the lowerlayer 41 and with 6160 Å in the via hole.

FIG. 5A shows the number of defects in accordance with the taper angleof the via hole or contact hole. Referring to FIG. 5A, the smaller thetaper angle of the via hole or the contact hole becomes, the fewerdefects in the element. It may be seen that when the taper angle of thecontact hole or via hole is 60° or less, an initial defect becomessignificantly reduced, thereby enabling fabrication of a more reliableelement. In this case, the initial defect may include a defect such as adark pixel that occurred before driving the OLED. When the taper angleof the via hole or contact hole is 60°, the thickness d2 of a portionwhere the taper reducing layer 43 is formed on the lower layer 41becomes 1000 Å and the thickness d3 of a portion where the taperreducing layer 43 is formed in the opening becomes 4000 Å, from theequations 5 and 6,

FIG. 5B shows a relationship between the taper angle θ2 and thethickness d3 of the taper reducing layer formed in the opening when thelower layer 41 formed on the substrate has a predetermined taper angleθ1 and a step d1. Referring to FIG. 5B, when the 6000 Å thick lowerlayer 41 has a taper angle of 75° and the taper reducing layer 43 isformed with a thickness d1 of at least 8000 Å to planarize the substratesurface, the taper angle θ2 of the opening should be 40° or less when apixel defining layer exists, and the taper angle θ2 of the contact holeor via hole should be is 60° or less when a pixel defining layer doesnot exist, in order to fabricate a reliable element.

To reduce the taper angle of the taper reducing layer as an organiclayer having a planarizing characteristic, as well as to prevent lightemitting characteristic from deteriorating in accordance with usage ofthe taper reducing layer, a high increase in driving voltage should beavoided when the taper reducing layer 43 is formed with a thickness d2of about 1000 Å to about 2000 Å on the lower layer 41.

Thus, the taper reducing layer used in an exemplary embodiment of thepresent invention preferably has a planarizing characteristic, a chargetransporting capability for transporting a hole or an electron, and aproper HOMO (highest occupied molecular orbital) and LUMO (lowestunfilled molecular orbital), so that it does not increase the drivingvoltage of the element due to an increased deposition thickness of thetaper reducing layer.

In the case of a typical bottom-emitting or top-emitting OLED, where thetaper reducing layer is formed below the emission layer and over theanode electrode, an organic layer having a hole transporting capabilitymay be used, with an HOMO of 4.5 eV or more, and charge mobility of 10⁻⁸cm²/Vs or more for the taper reducing layer. In the case of aninverted-type OLED, where the taper reducing layer is formed over thecathode electrode and below the emission layer, an organic layer havingan electron transporting capability may be used, with an LUMO of 3.5 eVor less, and charge mobility of 10⁻⁸ cm²/Vs or more for the taperreducing layer.

Referring to FIG. 4, the taper reducing layer is employed to aninsulating layer having an opening to reduce a taper angle. However, thetaper angle may be reduced by the taper reducing layer even in a steppedportion of the deposition layer, so that element defects may beprevented.

FIG. 6A shows a cross-sectional view of a bottom-emitting OLED having ataper reducing layer in accordance with an embodiment of the presentinvention. Referring to FIG. 6A, a buffer layer 405 is formed on aninsulating substrate 400, and a semiconductor layer 410, having sourceand drain regions 411 and 415, is formed on the buffer layer 405. A gate425 is formed on a gate insulating layer 420, and source and drainregions 441 and 445 are connected to the source and drain regions 411and 415 through contact holes 431 and 435 on an inter-layer insulatinglayer 430. Wiring 447, such as a data line or a power supply line, isformed at the same time the source and drain electrodes 441 and 445 areformed on the inter-layer insulating layer 430. The contact holes 431and 435 have a taper angle of 75° and a depth of 5000 Å.

An anode electrode 470, as a lower electrode connected to one of thesource and drain electrodes 441 and 445, for example, to the drainelectrode 445 through the via hole 455, is formed on a passivation layer450. The via hole 455 may have a taper angle of 85° and a depth of 5000Å, and the anode electrode 470 may have a thickness of 1000 Å. Afterforming the anode electrode 470, a cleaning process is performed. Ataper reducing layer 480, an organic film layer 485 and a cathodeelectrode 490 may be sequentially formed on the substrate.

FIG. 6B illustrates a cross-sectional view of an emission region of an Rpixel in an OLED in accordance with an embodiment of the presentinvention. Referring to FIG. 6B, the taper reducing layer 480 is formedon the anode electrode 470, and an emission layer 485 c is formed on thetaper reducing layer 480.

By way of an exemplary embodiment, a polymer organic layer having a holetransporting capability, such as, for example, PEDOT is formed with athickness of 1000 Å on the anode electrode 470 by a spin coating method,and an annealing process is performed by using a hot plate for 5 minutesat 200 Å, thereby forming the taper reducing layer 480. In this case,the deposition thickness of the taper reducing layer 480 is determinedby its taper angle, the depths and taper angles of the contact hole andvia hole below the taper reducing layer, the thickness of the pixelelectrode and a taper angle at an edge of the pixel electrode.

Using a vacuum deposition method, a 600 Å thick CuPc, as the holeinjecting layer 485 a, and a 300 Å thick NPB, as the hole transportinglayer 485 b, are sequentially formed on the taper reducing layer 480. A200 Å thick Alq+DCM, as the red color emission layer 485 c, is depositedon the hole transporting layer 485 b, and a 200 Å thick Alq₃, as theelectron transporting layer 485 d, is formed on the red emission layer485 c, thereby forming the organic film layer 485. In the presentembodiment, a hole blocking layer between the red color emission layer485 c and the electron transporting layer 485 d, and an electroninjecting layer on the electron transporting layer 485 d may be formed.Finally, LiF/Al, as the cathode electrode 490, is deposited by a thermalevaporation method.

After forming the organic film layer 485 and the cathode electrode 490,as shown in FIG. 6B, a sealant (not shown in the figures) is applied onthe insulating substrate 400 to prevent external oxygen and moisturefrom being introduced inside. An encapsulating substrate is bondedthereon, thereby fabricating the OLED.

FIG. 6C illustrates another cross-sectional view of the emission regionof the R pixel in the OLED in accordance with an embodiment of thepresent invention. Referring to FIG. 6C, the taper reducing layer 480 isformed between the emission layer 485 c and the hole transporting layer485 b of the organic film layer 485.

The anode electrode 470 is formed on the insulating layer 400, and thehole injecting layer 485 a and the hole transporting layer 485 b of theorganic film layer 485 are sequentially formed on the anode electrode470. The taper reducing layer 480 is formed on the hole transportinglayer 485 b, the R emission layer 485 c and the electron transportinglayer 485 d, as the organic emission layer 485 are sequentially formedon the taper reducing layer 480. The cathode electrode 490 is formed onthe electron transporting layer 485 d.

The taper reducing layer 480 may be formed just on the anode electrode470 and below the emission layer 485 c, as shown in FIGS. 6B and 6C, andat the same time, may be formed only between the anode electrode 470 andthe emission layer 485 c of the organic film layer 485. The organic filmlayer 485 has at least one of a hole injecting layer, a holetransporting layer, an emission layer, a hole blocking layer, anelectron transporting layer and/or an electron injecting layer.

In the first exemplary embodiment, the contact hole and via hole havetaper angles (θ41, θ42) of 75° and 85°, respectively, before forming thetaper reducing layer 480. The taper angle is reduced with respect to thesubstrate surface after the taper reducing layer 480 is formed, so thatthe taper angles (θ43, θ44) of the contact hole and via hole are 60° orless. The anode electrode has an edge taper angle θ47 and the taperreducing layer 480 may reduce the edge taper angle θ45 to 40°. Inaddition, the taper angle θ46 may be reduced near the contact hole, andvia hole and near the wiring 447 in accordance with formation of thetaper reducing layer.

The deposition thickness of the taper reducing layer 480 is determinedby the taper angle of the taper reducing layer, the depths and taperangles of the contact hole and via hole below the taper reducing layer,the thickness of the pixel electrode and the taper angle at an edge ofthe pixel electrode. When the taper reducing layer is deposited to havethe taper angles of the contact hole or via hole of 60° or less, fromFIG. 4 and equations 4 to 6, the deposition thickness of the taperreducing layer is determined by the taper angle of the contact hole andthe thickness of the insulating layer, such as the inter-layerinsulating layer and the gate insulating layer where the contact hole isformed, and further determined by the taper angle of the via hole andthe thickness of the insulating layer, such as the passivation layerwhere the via hole is formed. In the meantime, when the taper reducinglayer is deposited to have the taper angle at an edge of the pixelelectrode of 40° or less, the deposition thickness of the taper reducinglayer is determined by the taper angle at an edge of the pixel electrodeand the thickness of the pixel electrode, from FIG. 4 a and equations 4to 6.

FIG. 7A illustrates a SEM picture near the via hole in the OLED inaccordance with a first exemplary embodiment of the present invention.Referring to FIG. 7A, a portion with a thickness d73 where the taperreducing layer is formed on the anode electrode within the via hole isdeposited thicker than a portion with a thickness d72 where the taperreducing layer is formed on the anode electrode over an insulating layerhaving a stepped portion, so that the taper angle in the via hole isreduced to 50°. FIG. 7B illustrates a microscope picture forrepresenting whether edge defects occur in the emission region when theOLED of the first exemplary embodiment is driven. Referring to FIG. 7B,when the substrate surface is planarized by the taper reducing layer, sothat the taper angle is reduced at an edge of the pixel, defects may bereduced or eliminated at an edge of the emission region. FIG. 7Cillustrates a microscope picture for representing whether the edgedefects occur at an edge of the emission region when the OLED having thesame structure as shown in FIGS. 1A and 1B is driven. Referring to FIG.7C, it may be seen that dark spots may occur at an edge of the emissionregion when the taper reducing layer is not used. In this case, anumerical reference 71 indicates the dark spot near the via hole, and 72indicates the dark spot near the contact hole.

FIG. 8 illustrates a cross-sectional view of a bottom-emitting OLED inaccordance with a second exemplary embodiment of the present invention.Referring to FIG. 8, a buffer layer 505 is formed on an insulatingsubstrate 500, and a semiconductor layer 510 having source and drainregions 511 and 515 is formed on the buffer layer 505. A gate 525 isformed on a gate insulating layer 520, and source and drain electrodes541 and 545 are formed on an inter-layer insulating layer 530 throughcontact holes 531 and 535. In this case, a data line 547 is formed atthe same time when the source and drain electrodes 541 and 545 areformed on the inter-layer insulating layer 530.

An anode electrode 570 as a lower electrode connected to one of thesource and drain electrodes 541 and 545, such as, for example, to thedrain electrode 545 through the via hole 555, is formed on thepassivation layer 550. After depositing a 5000 Å thick pixel defininglayer 565 over the entire substrate, this pixel defining layer is etchedto have a taper angle θ51 of 60° to form an opening 575. After formingthe pixel defining layer 565, an organic layer, such as PEDOT, coated bya wet coating method and having a hole transporting capability, isdeposited on the substrate, so that a taper reducing layer 580 isformed. In this case, the taper reducing layer 580 may have a taperangle θ51 of the opening 575 of 40° or less, and the depositionthickness of the taper reducing layer 580 is determined by the taperangle of the taper reducing layer 580, thickness of the pixel defininglayer 585 and the taper angle of the opening 575.

After depositing the organic film layer 585 on the taper reducing layer580, such as in the first embodiment of FIG. 6A, and depositing LiF/Alfor the cathode electrode 590 on the organic film layer 585 by thethermal evaporation method, an encapsulating substrate (not shown) isthen bonded to fabricate the OLED in accordance with second exemplaryembodiment of the present invention.

FIG. 9A illustrates a SEM picture near an emission region of an OLED inaccordance with a second exemplary embodiment. Referring to FIG. 9A, itmay be seen that the taper angle at an edge of the opening is reduced to40° as the taper reducing layer is formed.

FIG. 9B illustrates a microscope picture of an edge of the emissionregion when the OLED employing the taper reducing layer in accordancewith the second exemplary embodiment is driven. Referring to FIG. 9B, itmay be seen that defects, such as a dark spot at an edge of the emissionregion, may be reduced or eliminated by forming the taper reducing layeron the pixel defining layer. FIG. 9C illustrates a microscope picture atan edge of the emission region when the OLED, having the pixel defininglayer and employing a conventional taper reducing layer, is driven.Referring to FIG. 9C, it may be seen that dark spots occur if the taperangle at an edge of the opening is large even when the pixel defininglayer is used.

FIG. 10 illustrates a cross-sectional view of a top-emitting OLED inaccordance with a third exemplary embodiment of the present invention.Referring to FIG. 10, a buffer layer 605 is formed on an insulatinglayer 600, and a semiconductor layer 610 having source and drain regions611 and 615 is formed on the buffer layer 605. A gate 625 is formed on agate insulating layer 620, and source and drain electrodes 641 and 645are formed on an inter-layer insulating layer 630 through contact holes631 and 635. In this case, wiring 647, such as a data line or a powersupply line, is formed when the source and drain electrodes 641 and 645are formed on the inter-layer insulating layer 630.

A planarization layer 660 is formed on a passivation layer 650, and ananode electrode 670 as a lower electrode connected to one of the sourceand drain electrodes 641 and 645, such as, for example, to the drainelectrode 645 through the via hole 655, is formed on the planarizationlayer 660. PEDOT as an organic layer that may be coated by a wet coatingmethod and has a hole transporting capability is deposited on thesubstrate, may be used so that the taper reducing layer 680 is formed.In this case, the taper reducing layer 680 may have the taper angle ofthe via hole of 60° or less, and the deposition thickness of the taperreducing layer 680 is determined by the taper angle of the taperreducing layer, thickness of the planarization layer 660 and the taperangle of the via hole.

After forming an organic film layer 685 and a cathode electrode 690 asan upper electrode on the taper reducing layer 680, such as in the firstexemplary embodiment, an encapsulating substrate (not shown in thefigure) is then used to fabricate the OLED in accordance with the thirdexemplary embodiment.

FIG. 11 illustrates a cross-sectional view of a top-emitting OLED inaccordance with a fourth exemplary embodiment of the invention.Referring to FIG. 11, a buffer layer 705 is formed on an insulatingsubstrate 700, and a semiconductor layer 710 having source and drainregions 711 and 715 is formed on the buffer layer 705. A gate 725 isformed on a gate insulating layer 720, and source and drain electrodes741 and 745 are formed on an inter-layer insulating layer 730 throughcontact holes 731 and 735. In this case, wiring 747 such as a data lineor a power supply line, is formed when the source and drain electrodes741 and 745 are formed on the inter-layer insulating layer 730.

A planarization layer 760 is formed on a passivation layer 750, and ananode electrode 770 as a lower electrode connected to one of the sourceand drain electrodes 741 and 745, such as, for example, to the drainelectrode 745 through the via hole 755, is formed on the planarizationlayer 760. A pixel defining layer 765, having an opening 775 forexposing a portion of the anode electrode 770, is then formed. PEDOT, asan organic layer that may be coated by a wet coating method and has ahole transporting capability, may be deposited on the substrate, so thatthe taper reducing layer 780 is formed. In this case, taper reducinglayer 780 may have the taper angle of the opening 775 of 40° or less,and the deposition thickness of the taper reducing layer 780 isdetermined by the taper angle of the taper reducing layer, the thicknessof the pixel defining layer and the taper angle of the pixel defininglayer. After forming a cathode electrode 790 for an upper electrode andan organic film layer 785 on the taper reducing layer 780, such as inthe first exemplary embodiment, an encapsulating substrate (not shown inthe figure) is used to fabricate the OLED in accordance with the fourthexemplary embodiment.

FIG. 12 illustrates a cross-sectional view of a bottom-emitting OLED inaccordance with a fifth exemplary embodiment of the present invention.Referring to FIG. 12, a buffer layer 805 is formed on an insulatingsubstrate 800, and a semiconductor layer 810 having source and drainregions 811 and 815 is formed on the buffer layer 805. A gate 825 isformed on a gate insulating layer 820, and source and drain electrodes841 and 845 are formed through contact holes 831 and 835 on aninter-layer insulating layer 830. In this case, an anode electrode 870is formed to be connected to one of the source and drain electrodes 841and 845, such as, for example, to the drain electrode 845 on theinter-layer insulating layer 830.

A passivation layer 850 having an opening 855 for exposing a portion ofthe anode electrode 870 is formed on the substrate. A taper reducinglayer 880 formed of a conductive organic layer that may be coated by awet coating method, such as, for example, PEDOT, is formed on theopening 855 and the passivation layer 850. The taper reducing layer 880may have a taper angle in the opening of 40° or less, and the thicknessof the taper reducing layer 880 is determined by the taper angle of thetaper reducing layer 880, the thickness of the passivation layer 850 andthe taper angle of the opening. After forming a cathode electrode 890for an upper electrode and an organic film layer 885 on the taperreducing layer 880, such as in the first exemplary embodiment, anencapsulating substrate (not shown in the figure) is bonded to fabricatethe OLED in accordance with the fifth exemplary embodiment.

In the exemplary embodiments of the present invention, the organic filmlayer has the hole injecting layer, the hole transporting layer, the R,G, or B organic emission layer and the electron transporting layer.However, it may have at least one of the hole injecting layer, the holetransporting layer, the R, G, or B organic emission layer, the holeblocking layer, the electron transporting layer and/or the electroninjecting layer.

In the exemplary embodiments of the present invention, top andbottom-emitting OLEDs, where the organic emission layer is deposited onthe anode electrode, use the organic layer having a hole transportingcapability for the taper reducing layer. However, it is also possible touse the organic layer having the electron transporting capability forthe taper reducing layer in the inverted-type OLED, where the organicemission layer is deposited on the cathode electrode.

In addition, the taper reducing layer is shown to be formed between theanode electrode and the organic film layer in the exemplary embodimentsof the present invention. However, it is possible to form the taperreducing layer on any layer existing between the emission layer of theorganic film layer and the anode electrode in the top andbottom-emitting OLEDs. It is also possible to form it on any layerexisting between the emission layer of the organic film layer and thecathode electrode in the inverted-type OLED.

In addition, the method for reducing the taper angle of the substratesurface by using the taper reducing layer of the present invention mayuse various methods, such as, for example, but not limited to, adeposition method, an inkjet method and a laser-induced thermal imagingfor forming the organic emission layer.

As mentioned above, by forming the organic film layer capable ofreducing the taper angle between the organic emission layer and thelower electrode in accordance with the exemplary embodiments of thepresent invention, defects near the contact hole and via hole and at astepped portion of the lower electrode and defects of the organicemission layer may be prevented, and reliability and the yield may alsobe improved.

While the present invention has been described with reference to variousexemplary embodiments, it is understood that the disclosure has beenmade for purpose of illustrating the invention by way of examples and isnot to limit the scope of the invention. One skilled in the art mayamend and change the exemplary embodiments of the present inventionwithout departing from the scope and spirit of the invention.

1. A flat panel display, comprising: an insulating substrate; a lowerlayer formed on the insulating substrate and having a first step and afirst taper angle with respect to a surface of the substrate; and anupper layer formed on the insulating substrate and for reducing thetaper angle of the lower layer, wherein the upper layer has a secondtaper angle smaller than the first taper angle of the lower layer. 2.The flat panel display of claim 1, wherein the upper layer is depositedthinner on a stepped portion than on the remaining portion to reduce thestep of the substrate surface.
 3. The flat panel display of claim 1,wherein the upper layer includes a conductive layer that has a chargetransporting capability and can be coated by a wet coating method. 4.The flat panel display of claim 3, wherein the upper layer includes atleast one layer selected from a group consisting of a polymer organiclayer and a small-molecule organic layer.
 5. The flat panel display ofclaim 4, wherein the small-molecule organic layer of the upper layer isselected from a group consisting of carbazole-based, arylamine-based,hydrazone-based, stilbene-based, oxadiazole-based and starburst-basedderivatives, and the polymer organic layer is selected from PEDOT, PANI,carbazole-based, arylamine-based, perylene-based, pyrrole-based andoxadiazole-based derivatives.
 6. The flat panel display of claim 1,wherein the lower layer further includes a hole for exposing a portionof the substrate, and the first taper angle is the angle between a sideof the hole and the substrate surface, and the second taper angle is theangle between the upper layer and the substrate surface in the hole. 7.The flat panel display of claim 6, further comprising a thin filmtransistor including source and drain regions, source and drainelectrodes and an insulating layer which is provided with a contact holefor connecting source and drain electrodes to the source and drainregions, wherein the lower layer is the insulating layer of the thinfilm transistor, and the hole is the contact hole for connecting thesource and drain electrodes to the source and drain regions.
 8. The flatpanel display of claim 6, further comprising a thin film transistorhaving at least the source and drain electrodes, a via hole for exposingone of the source and drain electrodes and a pixel electrode connectedto one of the exposed electrodes through the via hole, wherein the lowerlayer is the insulating layer, and the hole is the via hole forconnecting one of the exposed electrodes to the pixel electrode.
 9. Theflat panel display of claim 6, wherein the second taper angle is at 60°or less.
 10. The flat panel display of claim 1, further comprising anopening for exposing a portion of the substrate, wherein the first taperangle is the angle between a side of the opening and the substratesurface, and the second taper angle is the angle between the upper layerand the substrate surface in the opening.
 11. The flat panel display ofclaim 10, wherein the second taper angle is at 40° or less.
 12. The flatpanel display of claim 10, further comprising a lower electrode, a pixeldefining layer for exposing a portion of the lower electrode, an organicfilm layer, and an upper electrode, wherein the lower layer is the pixeldefining layer, and the opening exposes a portion of the lowerelectrode.
 13. The flat panel display of claim 12, wherein the upperlayer includes a conductive layer that has a charge transportingcapability and may be coated by a wet coating method.
 14. The flat paneldisplay of claim 13, wherein the upper layer includes at least oneselected from a group consisting of a polymer organic layer and asmall-molecule organic layer.
 15. The flat panel display of claim 14,wherein the small-molecule organic layer of the upper layer is selectedfrom a group consisting of carbazole-based, arylamine-based,hydrazone-based, stilbene-based, starburst-based, oxadiazole-based andstarburst-based derivatives, and the polymer organic layer is selectedfrom PEDOT, PANI, carbazole-based, arylamine-based, perylene-based,pyrrole-based and oxadiazole-based derivatives.
 16. The flat paneldisplay of claim 12, wherein the organic film layer has at least oneselected from a group consisting of a hole injecting layer, a holetransporting layer, an emission layer, a hole blocking layer, anelectron transporting layer and an electron injecting layer.
 17. Theflat panel display of claim 16, wherein the upper layer is formedbetween the lower electrode and the emission layer.
 18. The flat paneldisplay of claim 17, wherein the emission layer is selected from a groupconsisting of an organic film layer formed by a laser-induced thermalimaging, an organic film layer formed by an inkjet method, and anorganic film layer formed by a deposition method.
 19. The flat paneldisplay of claim 17, wherein the lower electrode is a transparentelectrode and the upper electrode is a reflective electrode, and lightemitted from the emission layer is directed toward the insulatingsubstrate.
 20. The flat panel display of claim 17, wherein the lowerelectrode is a reflective electrode and the upper electrode is atransparent electrode, and light emitted from the emission layer isdirected toward the opposite direction of the insulating substrate. 21.The flat panel display of claim 17, wherein both of the lower and upperelectrodes are transparent electrodes, and light emitted from theemission layer is directed toward the insulating substrate and towardthe opposite direction of the insulating substrate at the same time. 22.The flat panel display of claim 12, wherein the upper layer is anorganic film layer that has a hole transporting capability, a highestoccupied molecular orbital of at least 4.5 eV and a charge mobility ofat least 10⁻⁸ cm²/Vs.
 23. The flat panel display of claim 12, whereinthe lower electrode is a cathode electrode and the upper layer has anelectron transporting capability, lowest unfilled molecular orbital ofat least 3.5 eV, and a charge mobility of at least 10⁻⁸ cm²/Vs.
 24. Aflat panel display, comprising: an insulating substrate including a thinfilm transistor having at least source and drain electrodes; aninsulating layer formed on the insulating substrate and having a viahole for exposing one of the source and drain electrodes; an organic ELelement formed on the insulating layer and connected to the exposed oneelectrode through the via hole, and having a lower electrode, an organicfilm layer and an upper electrode; and a taper reducing layer formed onthe lower electrode, wherein a taper angle of the taper reducing layerin the via hole has a first taper angle smaller than that of the viahole, and a taper angle of the taper reducing layer at an edge of thelower electrode has a second taper angle smaller than that of the edgeof the lower electrode.
 25. The flat panel display of claim 24, whereinthe organic film layer includes at least one selected from a groupconsisting of a hole injecting layer, a hole transporting layer, anemission layer, a hole blocking layer, an electron transporting layerand an electron injecting layer, and the emission layer is any oneselected from a group consisting of an organic film layer formed by alaser-induced thermal imaging, an organic film layer formed by an inkjetmethod, and an organic film layer formed by a deposition method.
 26. Theflat panel display of claim 25, wherein the taper reducing layer is aconductive organic layer that can be coated by a wet coating method andhas a charge transporting capability, and is formed between the upperelectrode and the emission layer.
 27. The flat panel display of claim26, wherein the taper reducing layer includes at least one selected froma group consisting of a small-molecule organic layer selected fromcarbazole-based, arylamine-based, hydrazone-based, stilbene-based,oxadiazole-based and starburst-based derivatives, and a polymer organiclayer selected from PEDOT, PANI, carbazole-based, arylamine-based,perylene-based, pyrrole-based and oxadiazole-based derivatives.
 28. Theflat panel display of claim 24, wherein the first taper angle of thetaper reducing layer is 60° or less, and the second taper angle of thetaper reducing layer is 40° or less.
 29. The flat panel display of claim28, wherein the insulating layer includes at least one selected from agroup consisting of a passivation layer and a planarization layer, and adeposition thickness of the taper reducing layer is determined by thefirst and second taper angles of the taper reducing layer, a thicknessesof the passivation layer and the planarization layer, a taper angle ofthe via hole and a taper angle of an edge of an anode electrode.
 30. Theflat panel display of claim 24, wherein the lower electrode is areflective electrode, the upper electrode is a transparent electrode,and light emitted from the emission layer is directed toward theopposite direction of the insulating substrate, and the taper reducinglayer has a hole transporting capability, a highest occupied molecularorbital of at least 4.5 eV and a charge mobility of at least 10⁻⁸ cm²/Vswhen the lower electrode is an anode electrode, and has an electrontransporting capability, a lowest unoccupied molecular orbital of atleast 3.5 eV and a charge mobility of at least 10⁻⁸ cm²/Vs when thelower electrode is a cathode electrode.
 31. A flat panel display,comprising: an insulating substrate including a thin film transistorhaving at least source and drain electrodes; a first insulating layerformed on the insulating substrate and having a via hole for exposingone of the source and drain electrodes; a lower electrode formed on thefirst insulating layer and connected to the exposed one electrodethrough the via hole; a second insulating layer having an opening forexposing a portion of the lower electrode; an organic film layer formedon the second insulating layer and the opening; an upper electrodeformed on the organic film layer; and a taper reducing layer formed onthe lower electrode, wherein the taper reducing layer has a taper anglesmaller than that of the second insulating layer in the opening.
 32. Theflat panel display of claim 31, wherein the organic film layer includesat least one selected from a group consisting of a hole injecting layer,a hole transporting layer, an emission layer, a hole blocking layer, anelectron transporting layer and an electron injecting layer, and theemission layer is one selected from a group consisting of an organicfilm layer formed by a laser-induced thermal imaging, an organic filmlayer formed by an inkjet method and an organic film layer formed by adeposition method.
 33. The flat panel display of claim 32, wherein thetaper reducing layer is a conductive organic layer that can be coated bya wet coating method and has a charge transporting capability, and isformed between the upper electrode and the emission layer.
 34. The flatpanel display of claim 33, wherein the taper reducing layer includes atleast one of a small-molecule organic layer selected from a groupconsisting of carbazole-based, arylamine-based, hydrazone-based,stilbene-based, oxadiazole-based and starburst-based derivatives, and apolymer organic layer selected from PEDOT, PANI, carbazole-based,arylamine-based, perylene-based, pyrrole-based and oxadiazole-basedderivatives.
 35. The flat panel display of claim 31, wherein the taperangle of the taper reducing layer is 40° or less.
 36. The flat paneldisplay of claim 31, wherein the first insulating layer includes atleast one selected from a group consisting of a passivation layer and aplanarization layer; the second insulating layer includes a pixeldefining layer; and a deposition thickness of the taper reducing layeris determined by the taper angle of the taper reducing layer, and athickness and taper angle of the pixel defining layer.
 37. The flatpanel display of claim 31, wherein the lower electrode is a reflectiveelectrode and the upper electrode is a transparent electrode, and lightemitted from the emission layer is directed toward the oppositedirection of the insulating substrate, and the taper reducing layer hasa hole transporting capability, a highest occupied molecular orbital ofat least 4.5 eV and a charge mobility of at least 10⁻⁸ cm²/Vs when thelower electrode is an anode electrode, and an electron transportingcapability, a lowest unoccupied molecular orbital of at least 3.5 eV anda charge mobility of at least 10⁻⁸ cm²/Vs when the lower electrode is acathode electrode.
 38. A flat panel display, comprising: an insulatingsubstrate including a thin film transistor, the thin film transistorincluding a semiconductor layer having source and drain regions, a firstinsulating layer having a contact hole for exposing a portion of thesource and drain regions and source and drain electrodes connected tothe source and drain regions through the contact hole; a secondinsulating layer formed on the insulating substrate and having a viahole for exposing one of the source and drain electrodes; anelectroluminesence element formed on the second insulating layer andconnected to one electrode of the thin film transistor through the viahole, and having a lower electrode, an organic film layer and an upperelectrode; and a taper reducing layer formed on the lower electrode,wherein a taper angle of the taper reducing layer in the contact holehas a first taper angle smaller than that of the contact hole, a taperangle of the taper reducing layer in the via hole has a second taperangle smaller than that of the via hole, and a taper angle of the taperreducing layer at an edge of the lower electrode has a third taper anglesmaller than that of the edge of the lower electrode.
 39. The flat paneldisplay of claim 38, wherein the organic film layer includes at leastone selected from a group consisting of a hole injecting layer, a holetransporting layer, an emission layer, a hole blocking layer, anelectron transporting layer and an electron injecting layer, and theemission layer is one organic layer selected from a group consisting ofan organic film layer formed by a laser-induced thermal imaging, anorganic film layer formed by an ink-jet method, and an organic filmlayer formed by a deposition method.
 40. The flat panel display of claim39, wherein the taper reducing layer is a conductive organic layer thatcan be coated by a wet coating method and has a charge transportingcapability, and formed between the upper electrode and the emissionlayer.
 41. The flat panel display of claim 40, wherein the taperreducing layer consists of at least one selected from the groupconsisting of a small-molecule organic layer selected fromcarbazole-based, arylamine-based, hydrazone-based, stilbene-based,oxadiazole-based and starburst-based derivatives, and a polymer organiclayer selected from PEDOT, PANI, carbazole-based, arylamine-based,perylene-based, pyrrole-based and oxadiazole-based derivatives.
 42. Theflat panel display of claim 38, wherein the first, second, and thirdtaper angles are 60° or less, 60°or less and 40° or less, respectively.43. The flat panel display of claim 38, wherein the insulating layerconsists of any one selected from a group consisting of a passivationlayer and a planarization layer, and a deposition thickness of the taperreducing layer is determined by the first, second and third taper anglesof the taper reducing layer, a thickness of the insulating layer, taperangles of the via hole and contact hole, a thickness of the lowerelectrode and a taper angle at an edge of the lower electrode.
 44. Theflat panel display of claim 38, wherein the lower electrode is atransparent electrode, the upper electrode is a reflective electrode,and light emitted from the emission layer is directed toward theinsulating substrate, and the taper reducing layer has a holetransporting capability, a highest occupied molecular orbital of atleast 4.5 eV and a charge mobility of at least 10⁻⁸/cm²/Vs when thelower electrode is an anode electrode, and has an electron transportingcapability, a lowest occupied molecular orbital of at least 3.5 eV and acharge mobility of at least 10⁻⁸/cm² Vs when the lower electrode is acathode electrode.
 45. A flat panel display, comprising: an insulatingsubstrate including a thin film transistor, the thin film transistorincluding a semiconductor layer having source and drain regions, a firstinsulating layer having a contact hole for exposing some portions of thesource and drain regions, and source and drain electrodes connected tothe source and drain regions through the contact hole; a secondinsulating layer formed on the insulating substrate and having a viahole for exposing one of the source and drain electrodes; a lowerelectrode formed on the second insulating layer and connected to theexposed one electrode of the source and drain electrodes; a thirdinsulating layer having an opening for exposing a portion of the lowerelectrode; an organic film layer formed on the third insulating layerand the opening; an upper electrode formed on the organic film layer;and a taper reducing layer formed on the lower electrode, wherein ataper angle of the taper reducing layer in the opening is smaller thanthat of the opening.
 46. The flat panel display of claim 45, wherein theorganic film layer includes at least one selected from a groupconsisting of a hole injecting layer, a hole transporting layer, anemission layer, a hole blocking layer, an electron transporting layerand an electron injecting layer, and the emission layer is one selectedfrom a group consisting of an organic film layer formed by alaser-induced thermal imaging, an organic film layer formed by an inkjetmethod and an organic film layer formed by a deposition method.
 47. Theflat panel display of claim 46, wherein the taper reducing layer is aconductive organic layer that can be coated by a wet coating method andhas a charge transporting capability, and is formed between the upperelectrode and the emission layer.
 48. The flat panel display of claim47, wherein the taper reducing layer includes at least one of asmall-molecule organic layer selected from a group consisting ofcarbazole-based, arylamine-based, hydrazone-based, stilbene-based,oxadiazole-based and starbust-based derivatives, and a polymer organiclayer selected from PEDOT, PANI, carbazole-based, arylamine-based,perylene-based, pyrrole-based and oxadiazole-based derivatives.
 49. Theflat panel display of claim 45, wherein the taper angle of the taperreducing layer is 40° or less.
 50. The flat panel display of claim 45,wherein the first insulating layer is an inter-layer insulating layer,and the second insulating layer includes at least one selected from agroup consisting of a passviation layer and a planarization layer, andthe third insulating layer includes a pixel defining layer, and adeposition thickness of the taper reducing layer is determined by thetaper angle of the taper reducing layer and a thickness and taper angleof the pixel defining layer.
 51. The flat panel display of claim 45,wherein the lower electrode is a transparent electrode and the upperelectrode is a reflective electrode, and light emitted from the emissionlayer is directed toward the insulating substrate, and the taperreducing layer has a hole transporting capability, a highest occupiedmolecular orbital of at least 4.5 eV and a charge mobility of at least10⁻⁸ cm²/Vs when the lower electrode is an anode electrode, and has anelectron transporting capability, a lowest occupied molecular orbital ofat least 3.5 eV and charge mobility of at least 10⁻⁸ cm²/Vs when thelower electrode is a cathode electrode.
 52. A flat panel display,comprising: an insulating substrate including a thin film transistor,the thin film transistor including a semiconductor layer having sourceand drain regions, a first insulating layer having a contact hole forexposing some portions of the source and drain regions and a thin filmtransistor having source and drain electrodes connected to the sourceand drain regions through the contact hole; a lower electrode formed onthe same first insulating layer as the source and drain electrodes andconnected to one of the source and drain electrodes; a second insulatinglayer having an opening for exposing a portion of the lower electrode;an organic film layer formed on the second insulating layer and theopening; an upper electrode formed on the organic film layer; and ataper reducing layer formed on the lower electrode, wherein a taperangle of the taper reducing layer in the contact hole have a first taperangle smaller than that of the contact hole, and a taper angle of thetaper reducing layer in the opening has a second taper angle smallerthan that of the opening.
 53. The flat panel display of claim 52,wherein the organic film layer includes at least one selected from agroup consisting of a hole injecting layer, a hole transporting layer,an emission layer, a hole blocking layer, an electron transporting layerand an electron injecting layer, and the emission layer is one selectedfrom a group consisting of an organic film layer formed by alaser-induced thermal imaging, an organic film layer formed by an inkjetmethod and an organic film layer formed by a deposition method.
 54. Theflat panel display of claim 53, wherein the taper reducing layer is aconductive organic layer that can be coated by a wet coating method andhas a charge transporting capability, and is formed between the upperelectrode and the emission layer.
 55. The flat panel display of claim54, wherein the taper reducing layer consists of at least one selectedfrom a group consisting of a small-molecule organic layer and a polymerorganic layer, the small-molecule organic layer being selected fromcarbazole-based, arylamine-based, hydrazone-based, stilbene-based,oxadiazole-based and starburst-based derivatives, and the polymerorganic layer being selected from PEDOT, PANI, carbazole-based,arylamine-based, perylene-based, pyrrole-based and oxadiazole-basedderivatives.
 56. The flat panel display of claim 52, wherein the firsttaper angle of the taper reducing layer is 60° or less, and the secondtaper angle of the taper reducing layer is 40° or less.
 57. The flatpanel display of claim 52, wherein the first insulating layer is aninter-layer insulating layer, and the second insulating layer is apassivation layer, and a deposition thickness of the taper reducinglayer is determined by the first and second taper angles of the taperreducing layer, a thicknesses of the inter-layer insulating layer andthe passivation layer, and taper angles of the contact hole and opening.58. The flat panel display of claim 52, wherein the lower electrode is atransparent electrode and the upper electrode is a reflective electrode,and light emitted from the emission layer is directed toward theinsulating substrate, and the taper reducing layer has a holetransporting capability, a highest occupied molecular orbital of atleast 4.5 eV and a charge mobility of at least 10⁻⁸ cm²/Vs when thelower electrode is an anode electrode, and has an electron transportingcapability, a lowest unoccupied molecular orbital of at least 3.5 eV andcharge mobility of at least 10⁻⁸ cm²/Vs when the lower electrode is acathode electrode.
 59. A flat panel display, comprising: an insulatingsubstrate; a lower layer formed on the insulating layer and having afirst step and a first taper angle θ1 with respect to a surface of thesubstrate; and an upper layer formed on the insulating substrate andhaving a second taper angle θ2 for the substrate surface to reduce thefirst taper angle of the lower layer, wherein a deposition thicknessd0[zero] is the deposition thickness of the lower layer at the firststep, a deposition thickness d2 is the deposition thickness of the upperlayer on the first step and a deposition thickness d3 is the depositionthickness of upper layer at a portion other than the first step, and ataper angle θ2 of the upper layer are obtained from the equation below,tan θ2=(1−d 2/(d 1−d 0))tan θ1d 2=(d 1−d 0)(1−tan θ2/tan θ1)d 3=d 1(1−tan θ2/tan θ1), wherein d1 is a deposition thickness of theupper layer when the second taper angle θ2 of the upper layer becomes0°.
 60. The flat panel display of claim 59, further comprising a thinfilm transistor including source and drain regions, source and drainelectrodes and an insulating layer having a contact hole for connectingthe source and drain electrodes to the source and drain regions, whereinthe lower layer is an insulating layer of the thin film transistor, thehole is the contact hole for connecting the source and drain electrodesto the source and drain regions, and a deposition thickness of the taperreducing layer is obtained from the equation in accordance with a taperangle of the taper reducing layer and a depth and taper angle of thecontact hole.
 61. The flat panel display of claim 59, furthercomprising: a thin film transistor having at least source and drainelectrodes; a via hole for exposing one of the source and drainelectrodes; and a pixel electrode connected to the exposed one electrodethrough the via hole, wherein the lower layer is the insulating layer,and the hole is the via hole for connecting the exposed one electrode tothe pixel electrode, and a deposition thickness of the taper reducinglayer is obtained from the equation in accordance with a taper angle ofthe taper reducing layer, and depth and taper angle of the via hole. 62.The flat panel display of claim 59, further comprising a lowerelectrode, a pixel defining layer for exposing a portion of the lowerelectrode, an organic film layer and an upper electrode, wherein thelower layer is the pixel defining layer, and the opening is one forexposing some portion of the lower electrode, and a deposition thicknessof the taper reducing layer is obtained from the equation in accordancewith a taper angle of the taper reducing layer, a thickness of the pixeldefining layer and a taper angle of the opening.
 63. The flat paneldisplay of claim 59, wherein the upper layer is a conductive organiclayer that cam be coated by a wet coating method has a chargetransporting capability, and includes of at least one selected from thegroup consisting of a small-molecule organic layer and a polymer organiclayer, the small-molecule organic layer being selected fromcarbazole-based, arylamine-based, hydrazone-based, stilbene-based,oxadiazole-based and starburst-based derivatives, and the polymerorganic layer being selected from PEDOT, PANI, carbazole-based,arylamine-based, perylene-based, pyrrole-based and oxadiazole-basedderivatives.